Recent device miniaturization (shrinkage of transistor dimensions) has caused a chip to be increased in size and density. This, in turn, has increased screening test time (wafer test at preprocess and a final test following packaging) and test cost to render it difficult to decrease a product cost. An increased chip size means an increased number of transistors and an increased number of combinations. An increased chip density means an increased number of transistors and an increased probability of defect per unit area. On the other hand, the physical phenomenon is becoming increasingly complex and the number of types
of defect is also increasing.
To provide for shorter test time, the technique of parallel testing of chips under test (devices under test, also termed as DUTs), shown for example in FIG. 16, has so far been used. A plural number of input/output ports of a tester (Automatic Test Equipment) 1 are divided into a plurality of groups. The input/output ports mean a set of drivers and comparators, and are also termed I/O channels or I/O pins. The chips under test 10 are connected to the respective groups and a plurality of chips under test 10-1 to 10-3 are simultaneously tested in parallel on the tester 1. During functional testing, test patterns (force patterns) are supplied in parallel from respective different groups of drivers, not shown, and outputs of the chips under test 10-1 to 10-3 are compared in parallel with expected value patterns by comparators of each of the different groups, such as to give decisions on pass/fail.
As regards a BOST (Built Out Self Test), subsequently explained in Examples of the present invention, reference may be made to, for example, the disclosure of Patent Document 1. In Patent Document 1, there is disclosed an arrangement in which test chips BIST (Built In Self Test) and BOST are used to conduct a pattern dependent testing and timing-dependent testing.    Patent Document 1: JP Patent Kokai JP-A-2003-16799    Non-Patent Document 1: Miura, N,; Mizoguchi, D.; Inoue M.; Niitsu, K.; Nakagawa, Y. Tago, M.; Fukaishi M.; Sakurai, T.; Kuroda, T., “A 1 Tb/s 3W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link”, Solid-State Circuits, IEEE Journal of, Volume 42, Issue 1, January 2007, Page(s): 111˜122